As a technique which has been studied by the present inventors, for example, the following technique has been considered regarding a semiconductor device including a phase change memory.
A storage element uses a chalcogenide material (or phase change material) such as Ge—Sb—Te-based or Ag—In—Sb—Te-based one containing at least antimony (Sb) and tellurium (Te) as materials for a storage layer. The characteristics of the phase change memory using the chalcogenide material are described, for example, in Non-Patent Document 1.
FIG. 2 is a graph illustrating a relationship between a pulse width and a temperature which are required for phase change of a resistive storage element using a phase change material. When storage information “0” is written in the resistive storage element, such a reset pulse as to heat the device up to a melting point Ta of a chalcogenide material or higher and to rapidly cool the same is applied to the device, as illustrated in FIG. 2. By setting a cooling time t1 short, for example, to about 1 ns, the chalcogenide material is changed to a high-resistance amorphous (noncrystalline) state.
On the contrary, when writing of storage information “1” is performed, the chalcogenide material is changed to a poly crystal state having a low resistance by applying such a set pulse as to hold the temperature of the resistive storage element in a temperature range lower than the melting point Ta and higher than a crystallization temperature Tx that is higher than or equal to a glass-transition temperature. A time required for crystallization t2 varies depending on the composition of the chalcogenide material. The temperature of the device illustrated in FIG. 2 depends on Joule heat which the resistive storage element itself generates and on thermal diffusion to the environment.
A typical phase change memory includes a memory-cell array MCA, a block of word drivers WDB, a multiplexer MUX, a program circuit PRGM, and a sense amplifier SA, as illustrated in FIG. 3. The memory-cell array MCA includes memory cells MC00, MC10, . . . arranged in matrix at intersection points of word lines WL0, WL1, . . . and bit-lines BL0, BL1, . . . . The memory cell has a configuration in which the abovementioned resistive storage element RE and a select transistor CT are inserted between the bit-line BL0 and a ground terminal, for example, as illustrated in MC00. A gate electrode of the select transistor CT is connected to the word line WL0. The block of word drivers WDB selects one from the word lines WL0, WL1, . . . in response to an address signal (not illustrated). The multiplexer MUX selects one from the bit-lines BL0, BL1, . . . in response to an address signal (not illustrated) and connects the bit-line to the program circuit PRGM or the sense amplifier SA.
In Patent Document 1, a layout structure of a semiconductor memory device having a hierarchical structure and a layout method thereof are described. Specifically, the same structure as that of the memory cell is formed on a wiring area for a global bit-line and a regularity of a layout pattern of a structure in a memory-cell array is maintained. In Patent Document 2, such disposing a structure similar to that of the memory cell around a memory-cell array is described.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2006-295117    Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2004-349504    Patent Document 3: WO2005/117118    Non-Patent Document 1: “IEEE International Electron Devices meeting, TECHNICAL DIGEST,” (USA), 2001, pp. 803-806    Non-Patent Document 2: “IEEE International Solid-State Circuits Conference, Digest of Technical Papers,” (USA), 2007, pp. 472-473    Non-Patent Document 3: “IEEE International Solid-State Circuits Conference, Digest of Technical Papers,” (USA), 2007, pp. 474-475